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document number: mc33927 rev. 2.0, 8/2007 freescale semiconductor advance information * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2007. all rights reserved. three-phase field effect transistor pre-driver the 33927 is a field effect transistor (fet) pre-driver designed for three-phase motor control and similar applications. the integrated circuit (ic) uses smartmos ? technology. the ic contains three high-side fet pre-drivers and three low-side fet pre-drivers.three external bo otstrap capacitors provide gate charge to the high side fets. the ic interfaces to a mcu via six direct input control signals, a spi port for device setup and asynchronous reset, enable and interrupt signals. both 5.0v and 3.0v logic level inputs are accepted and 5.0v logic level outputs are provided. features ? fully specified from 8.0v to 40v covers 12v and 24v automotive systems ? extended operating range from 6.0v to 58v covers 12v and 42v systems ? 1.0a gate drive capability with protection ? protection against reverse charge injection from cgd and cgs of external fets ? includes a charge pump to support full fet drive at low battery voltages ? deadtime is programmable via the spi port ? simultaneous output capability enabled via safe spi command ? pb-free packaging designated by suffix code ek figure 1. 33927 simplified application diagram fet pre-driver ek suffix (pb-free) 98asa99334d 54-pin soicw-ep 33927 ordering information device temperature range (t a ) package mcz33927ek/r2 -40c to 125c 54 soicw-ep vpump pump vbat vpwr vls vdd px_hs px_ls phasex cs si sclk so rst int pa_hs_g pb_hs_g pc_hs_g pa_hs_s pb_hs_s pc_hs_s pa_ls_g pb_ls_g pc_ls_g pgnd_x amp_p amp_n amp_out gnd 33927 v bat mcu or dsp 3 3 3 r sen en1 vss en2
analog integrated circuit device data 2 freescale semiconductor 33927 internal block diagram internal block diagram figure 2. 33927 simplifi ed internal block diagram vpump pump vbat vpwr vls vdd px_hs px_ls phasex cs si sclk so rst int amp_p amp_n amp_out pgndx main charge pump pgnd en1 en2 oc_out gnd(2) px_boot px_hs_g px_hs_s px_ls_g oc_th vls_cap trickle charge pump hold -off circuit oscillator control logic 5v reg. vdd vls reg. uv detect t-lim + - + - + - 1.4v + - vbat vbat + - over-cur. comp. i-sense amp. high- side driver low- side driver 3 3 3 3x desat. comp phase comp. vss
analog integrated circuit device data freescale semiconductor 3 33927 pin connections pin connections figure 3. 33927 pin connections table 1. 33927 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 20 . pin pin name pin function formal name definition 1 phasea digital output phase a totem pole output of phase a comparator. this output is low when the voltage on pa_hs_s (source of high-side fet) is less than 50% of vbat 2 pgnd ground power ground power ground for charge pump 3 en1 digital input enable 1 logic signal input must be high (anded with en2) to enable any gate drive output. 4 en2 digital input enable 2 logic signal input must be high (anded with en1) to enable any gate drive output 5 rst digital input reset reset input 6, 33, 49, 50, 52, 53 n/c ? no connect these pins do not connect 7 pump power drive out pump charge pump output 8 vpump power input voltage pump charge pump supply 9 vbat digital input voltage battery battery supply 10 phaseb digital output phase b totem pole output of phase b comparator. this output is low when the voltage on pb_hs_s (source of high-side fet) is less than 50% of vbat 11 phasec digital output phase c totem pole output of phase c comparator. this output is low when the voltage on pc_hs_s (source of high-side fet) is less than 50% of vbat 54 40 .35 34 33 32 31 30 29 28 39 38 37 36 47 46 45 44 43 42 41 51 50 49 48 53 52 1 15 20 21 22 23 24 25 26 27 16 17 18 19 8 9 10 11 12 13 14 4 5 6 7 2 3 phasea pgnd en1 en2 rst n/c pump vpump vbat phaseb phasec pa_hs pa_ls vdd pb_hs pb_ls int cs si sclk so pc_ls pc_hs amp_out amp_n amp_p oc_out vpwr n/c n/c vls n/c n/c pa_boot pa_hs_g pa_hs_s pa_ls_g pgnda pb_boot pb_hs_g pb_hs_s pb_ls_g pgndb pc_boot pc_hs_g pc_hs_s pc_ls_g pgndc n/c vls_cap gnd1 gnd0 vss oc_th
analog integrated circuit device data 4 freescale semiconductor 33927 pin connections 12 pa_hs digital input phase a high-side active low input logic signal enables the high-side driver for phase a 13 pa_ls digital input phase a low-side active high input logic signal enables the low-side driver for phase a 14 vdd analog output vdd regulator vdd regulator output. internally generated 5v supply 15 pb_hs digital input phase b high-side active low input logic signal enables the high-side driver for phase b 16 pb_ls digital input phase b low-side active high input logic signal enables the low-side driver for phase b 17 int digital output interrupt interrupt pin output 18 cs digital input chip select chip select input. it frames spi commands and enables spi port 19 si digital input serial in input data for spi port. clocked on the falling edge of sclk, msb first 20 sclk digital input serial clock clock for spi port and typically is 3.0 mhz 21 so digital output serial out output data for spi port. tri-state until cs becomes low 22 pc_ls digital input phase c low-side active high input logic signal enables the low-side driver for phase c 23 pc_hs digital input phase c high-side active low input logic signal enables the high-side driver for phase c 24 amp_out analog output amplifier output output of the current-sensing amplifier 25 amp_n analog input amplifier invert inverting input of the current-sensing amplifier 26 amp_p analog input amplifier non-invert non-inverting input of the current-sensing amplifier 27 oc_out digital output overcurrent out totem pole digital output of the over-current comparator 28 oc_th analog input overcurrent threshold threshold of the overcurrent detector 29 vss ground voltage source supply ground reference for logic interface and power supplies 30, 31 gnd ground ground substrate and esd reference, connect to vss 32 vls_cap analog output vls regulator output capacitor vls regulator connection for additional output capacitor, providing low impedance supply source for low-side gate drive 34 pgndc power input phase c return gate current return for the low-side fets for phase c gate current 35 pc_ls_g power output phase c low-side gate drive gate drive output for phase c low-side 36 pc_hs_s power input phase c high-side source source connection for phase c high-side fet 37 pc_hs_g power output phase c high-side gate drive gate drive for output phase c high-side fet 38 pc_boot analog input phase c bootstrap bootstrap capacitor for phase c 39 pgndb power input phase b return gate current return for the low-side fets for phase b 40 pb_ls_g power output phase b low-side gate drive gate drive for output phase b low-side 41 pb_hs_s power input phase b high-side source source connection for phase b high-side fet 42 pb_hs_g power output phase b high-side gate drive gate drive for output phase b high-side 43 pb_boot analog input phase b bootstrap bootstrap capacitor for phase b 44 pgnda power input phase a return gate current return for the low-side fets for phase a 45 pa_ls_g power output phase a low-side gate drive gate drive for output phase a low-side table 1. 33927 pin definitions (continued) a functional description of each pin can be found in the functional pin description section beginning on page 20 . pin pin name pin function formal name definition
analog integrated circuit device data freescale semiconductor 5 33927 pin connections 46 pa_hs_s power input phase a high-side source source connection for phase a high-side fet 47 pa_hs_g power output phase a high-side gate drive gate drive for output phase a high-side 48 pa_boot analog input phase a bootstrap bootstrap capacitor for phase a 51 vls analog output vls regulator vls regulator output. power supply for the gate drives 54 vpwr power input voltage power power supply input for gate drives ep ground exposed pad device will perform as specifi ed with the exposed pad un-terminated (floating) however, it is recommended that the exposed pad be terminated to pin 29 (vss) and system ground table 1. 33927 pin definitions (continued) a functional description of each pin can be found in the functional pin description section beginning on page 20 . pin pin name pin function formal name definition
analog integrated circuit device data 6 freescale semiconductor 33927 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings vbat supply voltage normal operation (steady-state) transient survival (1) v bat 58 -1.5 to 80 v vpwr supply voltage normal operation (steady-state) transient survival (1) v pwr 58 -1.5 to 80 v charge pump (pump, vpump) v pump -0.3 to 40 v vls regulator outputs (vls , vls_cap) v ls -0.3 to 18 v logic supply voltage v dd -0.3 to 7.0 v logic output (int, so, phasea, phaseb, phasec, oc_out) (2) v out -0.3 to 7.0 v logic input pin voltage (en1, en2, px_hs , px_ls, si, sclk, cs , rst ) 10ma v in -0.3 to 7.0 v amplifier input voltage (both inputs-gnd), (amp_p - gnd) or (amp_n - gnd) 6ma source or sink v in_a -7.0 to 10.0 v over-current comparator threshold 10ma v oc -0.3 to 7.0 v driver output voltage (3) high-side bootstrap (pa_boot, pb_boot, pc_boot) high-side (pa_hs_g, pb_hs_g, pc_hs_g) low-side (pa_ls_g, pb_ls_g, pc_ls_g) v boot v hs_g v ls_g 75 75 16 v driver voltage transient survival high-side (pa_hs_g, pb_hs_g, pc_hs_g, pa_hs_s, pb_hs_s, pc_hs_s) low-side (pa_ls_g, pb_ls_g, pc_ls_g, pgnda, pgndb, pgndc) v hs_g v hs_s v ls_g v pgnd -7.0 -7.0 -7.0 -7.0 v continuous output current i gate -0.1 to 0.1 a esd voltage (4) human body model - hbm (all pins except for the pins listed below) pins: pa_boot, pa_hs_s, pa_h s_g, pb_boot, pb_hs_s, pb_hs_g, pc_boot, pc_hs_s, pc_hs_g, vpwr charge device model - cdm v esd 2000 1000 750 v notes 1. the device will withstand load dump transient as defined by iso7637 with peak voltage of 80v. 2. short-circuit proof, the device will not be damaged or induce unexpected behavior due to shorts to external sources within th is range. 3. this voltage should not be applied without also taking voltage at hs_s and voltage at pgnd_x into account. 4. esd testing is performed in accordance with the human body model (hbm) (c zap = 100pf, r zap = 1500 ? ) and the charge device model (cdm), robotic (c zap = 4.0pf).
analog integrated circuit device data freescale semiconductor 7 33927 electrical characteristics maximum ratings thermal ratings storage temperature t stg -55 to +150 c operating junction temperature t j -40 to +150 c thermal resistance (5) junction-to-case r jc 3.0 c/w soldering temperature (6) t solder note 7 c notes 5. case is considered ep - pin 55 under the body of the device. the actual power dissipation of the device is dependent on the o perating mode, the heat transfer characteristics of the board and layout and the operating voltage. see figure 19 and figure 20 for examples of power dissipation profiles of two common configurations. operation above the maximu m operating junction temperature will result in a reduction in reliability leading to malf unction or permanent damage to the device. 6. pin soldering temperature limit is for 10 seconds maximum dura tion. not designed for immersion so ldering. exceeding these lim its may cause malfunction or permanent damage to the device. 7. freescale?s package reflow capability meets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.freescale.com, search by part number [e.g. remove pref ixes/suffixes and enter the core id to view all orderable parts . (i.e. mc33xxxd enter 33xxx), and review parametrics. table 2. maximum ratings (continued) all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit
analog integrated circuit device data 8 freescale semiconductor 33927 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electr ical characteristics characteristics noted under conditions 8.0v v pwr =v bat 40v , -40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit power inputs vbat supply voltage startup threshold (8) v bat_st ? 6.0 8.0 v vbat supply current, v pwr = v bat = 40v rst and enable = 5.0v no output loads on gate drive pins, no pwm no output loads on gate driv e pins, 20khz, 50% duty cycle i bat ? ? 1.0 ? ? 10 ma vpwr supply current, v pwr = v bat = 40v rst and enable = 5.0v no output loads on gate drive pins, no pwm output loads = 620nc per fet, 20khz pwm (9) i pwr_on ? ? 11 ? 20 95 ma sleep state supply current, rst = 0v v bat = 40v v pwr = 40v i bat i pwr ? ? 14 56 30 100 a sleep state output gate voltage ig < 100a v gatess ? ? 1.3 v trickle charge pump (bootstrap voltage) v bat = 14v v boot 22 28 32 v bootstrap diode forward voltage at 10ma v f ? ? 1.2 v vdd v internal regulator v dd output voltage, v pwr = 8v to 40v, c = 0.47f (10) external load i dd_ext = 0 to 1.0ma v dd 4.5 ? 5.5 v internal v dd supply current, v dd = 5.5v, no external load i dd ? ? 12 ma vls regulator peak output current, v pwr = 16v, v ls = 10v i peak 350 600 800 ma linear regulator output voltage, i vls = 0 to 60ma (11) v ls 13.5 15 17 v vls disable threshold (12) v thvls 7.5 8.0 8.5 v notes 8. when minimum system voltage could be less than 14v operation with the charge pump is recommended. v bat must exceed this threshold in order for the charge pump and v dd regulator to startup and drive v pwr to > 8.0v. once v pwr exceeds 8.0v, the circuits will continue to operate even if v bat drops below 6.0v. 9. this parameter is guaranteed by design. it is not production tested. 10. minimum external capacitor for stable v dd operation is 0.47f. 11. recommended external capacitor for the v ls regulator is 2.2f low esr at each pin vls and vls_cap. 12. when v ls is less than this value, the outputs are disabled and holdoff ci rcuits are active.
analog integrated circuit device data freescale semiconductor 9 33927 electrical characteristics static electrical characteristics charge pump charge pump high-side switch on-resistance low-side switch on-resistance regulation threshold difference (13)(15) r ds(on)_hs r ds(on)_ls v threg ? ? 250 6.0 5.0 500 10 9.4 900 ? ? mv charge pump output voltage (14) , (15) i out = 40ma, 6.0v < v bat < 8.0v i out = 40ma, v bat > = 8.0v v cp 8.5 12 9.5 ? ? ? v gate drive high-side driver on-r esistance (sourcing) v pwr = v bat = 16v, -40 c t a 25 c v pwr = v bat = 16v, 25 c < t a 125 c r ds(on)_h_src ? ? ? ? 6.0 8.5 ? high-side driver on-r esistance (sinking) v pwr = v bat = 16v r ds(on)_h_sink ? ? 3.0 ? high-side current injection allowed without malfunction (15) , (16) i hs_inj ? ? 0.5 a low-side driver on-resistance (sourcing) v pwr = v bat = 16v, -40 c t a 25 c v pwr = v bat = 16v, 25 c < t a 125 c r ds(on)_l_src ? ? ? ? 6.0 8.5 ? low-side driver on-resistance (sinking) v pwr = v bat = 16 v r ds(on)_l_sink ? ? 3.0 ? low-side current injection allowed without malfunction (15) , (16) i ls_inj ? ? 0.5 gate source voltage, v pwr = v bat = 40v high-side, i gate = 0 (17) low-side, i gate = 0 v gs_h v gs_l 13 13 14.8 15.4 16.5 17 v high-side gate drive output leakage current, per output (18) i hs_leak ? ? 18 a notes 13. when vls is this amount below the normal vls li near regulation threshold, the pump is enabled. 14. with recommended external components (1.0f, mur 120 diode). t he charge pump is designed to supply the gate currents of a system with 100a fets in a 12v application. 15. this parameter is a design char acteristic, not production tested. 16. current injection only occurs during output switch transitions . the ic is immune to specified injected currents for a durati on of approximately 1 s after an output switch transition. 1 s is sufficient for all intended applications of this ic. 17. if a slightly higher gate voltage is required, larger bootst rap capacitors are required. at high duty cycles, the bootstrap voltage may not recover completely, leading to a higher outpu t on-resistance. this effect can be minimi zed by using low esr capacitors for the bootstrap and the vls capacitors. 18. a small internal charge pump will supply up to 30 a nominal to compensate for leakage on the high-side fet gate output and maintain voltages after bootstrap events. it is not intended for external components to be connected to the high-side fet gate, but smal l amounts of additional leakage can be accommodated. table 3. static electrical characteristics (continued) characteristics noted under conditions 8.0v v pwr =v bat 40v , -40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 10 freescale semiconductor 33927 electrical characteristics static electrical characteristics overcurrent comparator common mode input range v cm 2.0 ? v dd -0.02 v input offset voltage v os_oc -50 ? 50 mv overcurrent comparator threshold hysteresis (19) v oc_hyst 50 300 mv output voltage high-level at i oh = -500a low-level at i ol = 500a v oh v ol 0.85 v dd ? ? ? v dd 0.5 v hold off circuit v dd threshold (v dd falling) rst pin high v dd_th 1.5 ? 4.0 v hold off current (at each gate pin) 3.0v < v bat < 40v (20) i hold 10 ? 300 a phase comparator high-level input voltage threshold v ih_th 0.5 v bat ? 0.65 v bat v low-level input voltage threshold v il_th 0.3 v bat ? 0.45 v bat v high-level output voltage at i oh = -500a v oh 0.85 v dd ? v dd v low-level output voltage at i ol = 500a v ol ? ? 0.5 v high-side source input resistance (19) , (23) r in ? 50 ? k ? desaturation detector desaturation detector threshold (21) v des_th 1.2 1.4 1.6 v current sense amplifier recommended external series resistor (see figure 9 ) r s ? 1.0 ? k ? recommended external feedback resistor (see figure 9 ) limited by the output voltage dynamic range r fb 5.0 ? 15 k ? maximum input differential voltage (see figure 9 ) v id = v amp_p - v amp_n v id -800 ? +800 mv input common mode range (19) , (22) v c 0 ? 3.0 v input offset voltage r s = 1k ? , v cm = 0.0v v os -15 ? +15 mv input offset voltage drift (19) v os / t ? -10 ? v/c input bias current v cm = 2.0v i b -200 ? +200 na notes 19. this parameter is a design char acteristic, not production tested. 20. the hold off circuit is designed to oper ate over the full operating range of v bat . the specification indica tes the conditions used in production test. 21. desaturation is measured as the voltage drop below v bat , thus the threshold is compared to t he drain-source voltage of the external high-side fet. see figure 5 . 22. as long as one input is within v cm the output is guaranteed to have the correct phase. exceeding the common mode rails will not cause a phase inversion on the output. 23. input resistance is impedance from hi gh-side source and is referenced to ground. approximate tolerance is 20%. table 3. static electrical characteristics (continued) characteristics noted under conditions 8.0v v pwr =v bat 40v , -40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 11 33927 electrical characteristics static electrical characteristics current sense amplifier (continued) input offset current i os = i amp_p - i amp_n i os -80 ? +80 na input offset current drift (24) i os / t ? 40 ? pa/c output voltage high-level with r load = 10 k ? to v ss low-level with r load = 10 k ? to v dd v oh v ol v dd -0.2 ? ? ? v dd 0.2 v differential input resistance r i 1.0 ? ? m ? output short circuit current i sc 5.0 ? ? ma common-mode input capacitance at 10 khz (24)(25) c i ? ? 10 pf common-mode rejection ratio at dc cmrr = 20*log ((v out_diff /v in _ diff ) * (v in _ cm /v out _ cm )) cmrr 60 80 ? db large signal open loop voltage gain (dc) (24)(25) a ol ?60?db gain margin at gain = 5.0 (24)(25) a m ?5.0?db nonlinearity (24)(25) rl = 1k ? , c l = 500pf, 0.3 < v o < 4.8v, gain = 5.0 to 15 nl -1.0 ? +1.0 % notes 24. this parameter is a design char acteristic, not production tested. 25. without considering any offsets such as input offset voltage, internal mismatch and assuming no tolerance error in external resistors. table 3. static electrical characteristics (continued) characteristics noted under conditions 8.0v v pwr =v bat 40v , -40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 12 freescale semiconductor 33927 electrical characteristics static electrical characteristics supervisory and control circuits logic inputs (px_ls, px_hs , en1, en2) (27) high-level input voltage threshold low-level input voltage threshold v ih v il ? 0.9 ? ? 2.1 ? v logic inputs (si, sclk, cs ) (26) , (27) high-level input voltage threshold low-level input voltage threshold v ih v il ? 0.9 ? ? 2.1 ? v input logic threshold hysteresis (26) inputs px_ls, si, sclk, cs , px_hs , en1, en2 v ihys 100 250 450 mv input pull-down current, (px_ls, si, sclk, en1, en2) 0.3 v dd v in v dd i inpd 8.0 ? 18 a input pull-up current, (cs , px_hs ) (28) 0 v in 0.7 v dd i inpu 10 ? 25 a input capacitance (26) 0.0 v in 5.5v c in ? 15 ? pf rst threshold (29) v th_rst 1.0 ? 2.1 v rst pull-down resistance 0.3 v dd v in v dd r rst 40 60 85 k ? power-on rst threshold, (v dd falling) v thrst 3.4 4.0 4.5 v so high-level output voltage i oh = 1.0ma v soh 0.9 v dd ? ? v so low-level output voltage i ol = 1.0ma v sol ? ? 0.1 v dd v so tri-state leakage current cs = 0.7 v dd , 0.3 v dd = v so = 0.7 v dd i so_leak_t -1.0 ? 1.0 a so tri-state capacitance (26) , (30) 0.0 v in 5.5v c so_t ? 15 ? pf int high-level output voltage i oh = -500a v oh 0.85 v dd ? v dd % vdd int low-level output voltage i ol = 500a v ol ? ? 0.5 v thermal warning thermal warning temperature (26) , (31) t warn 150 170 185 c thermal hysteresis (26) t hyst 8 10 12 c notes 26. this parameter is guaranteed by design, not production tested. 27. logic threshold voltages derived re lative to a 3.3v 10% system. 28. pull-up circuits will no t allow back biasing of v dd. 29. there are two elements in the rst circuit: 1) one generally lower th reshold enables the internal regulator; 2) the second removes the reset from the internal logic. 30. this parameter applies to the off state (tri-stated) condi tion of so is guaranteed by desig n but is not production tested. 31. the thermal warning circuit does not forc e ic shutdown above this temperature. it is possible to set a bit in the mask regis ter to generate an interrupt when overtemperature is detected, and the stat us bits will always read bac k the state of the three indivi dual thermal warning circuits in the ic. table 3. static electrical characteristics (continued) characteristics noted under conditions 8.0v v pwr =v bat 40v , -40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 13 33927 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electr ical characteristics characteristics noted under conditions 8.0v v pwr = v bat 40v, -40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit internal regulators v dd power-up time (until int high) 8.0v v pwr (32) t pu_vdd ? ? 2.0 ms vls power-up time 16v v pwr (33) t pu_vdd ? ? 2.0 ms charge pump charge pump oscillator frequency f osc 90 125 190 khz charge pump slew rate (34) sr cp ? 100 ? v/ s gate drive high-side turn-on time transition time from 1.0 to 10v, load: c = 500pf, rg = 0, ( figure 7 ) t onh ? 20 35 ns high-side turn-on delay (35) delay from command to 1.0v, ( figure 7 ) t d_onh 130 265 386 ns high-side turn-off time transition time from 10 to 1.0v, load: c = 500pf, rg = 0, ( figure 8 ) t offh ? 20 35 ns high-side turn-off delay (35) delay from command to 10v, ( figure 8 ) t d_offh 130 265 386 ns low-side turn-on time transition time from 1.0 to 10v, load: c = 500pf, rg = 0, ( figure 7 ) t onl ? 20 35 ns low-side turn-on delay (35) delay from command to 1.0v, ( figure 7 ) t d_onl 130 265 386 ns low-side turn-off time transition time from 10 to 1.0v, load: c = 500pf, rg = 0, ( figure 8 ) t offl ? 20 35 ns low-side turn-off delay (35) delay from command to 10v, ( figure 8 ) t d_offl 130 265 386 ns same phase command delay match (36) t d_diff -20 0 +20 ns thermal filter duration (37) t dur 8.0 ? 30 s notes 32. the power-up time of the ic depends in part on the time requi red for this regulator to char ge up the external filter capacit or on v dd . 33. the power-up time of the ic depends in part on the time requir ed for this regulator to charge up the external filter capacit or on vls. this delay includes the expected time for v dd to rise. 34. the charge pump operating at 12v v bat , 1 f pump capacitor, mur120 diodes and 47 f filter capacitor. 35. these delays include all logic delays except deadtime. all inter nal logic is synchronous with t he internal clock. the total delay includes one clock period for state machine decision block, an additional cl ock period for fullon mux logi c, input synchronization time and output driver propagation delay. subtract one clock period for op eration in fullon mode which bypasses the state machine decisi on block. synchronization time accounts for up to one clock period of variation. see figure 6 . 36. this is the maximum separation or overlap of the high and low side gate drives due to propagation delays when commanding one on and the other off simultaneously. 37. the output of the overtemperature comparator goes through a digital filter before generating a warning or interrupt.
analog integrated circuit device data 14 freescale semiconductor 33927 electrical characteristics dynamic electrical characteristics gate drive (continued) duty cycle (38) , (39) t dc 0.0 ? 96 % 100% duty cycle duration (38) , (39) t dc ? ? unlimited s maximum programmable deadtime (40) t max 10.2 15 19.6 s overcurrent comparator overcurrent protection filter time t oc 0.9 ? 3.5 s rise time (oc_out) 10% - 90% c l = 100 pf t roc 10 ? 240 ns fall time (oc_out) 90% - 10% c l = 100 pf t foc 10 ? 200 ns phase comparator propagation delay time to 50% of v dd ; c l 100 pf rising edge delay falling edge delay t r t f ? ? ? ? 200 350 ns match conversion time (prop delay mismatch of three phases) c l = 100 pf (38) t match ? ? 100 ns desaturation detector desaturation and phase error blanking time t blank 4.0 ? 8.1 s filter time (38) fault must be present for this time to trigger t filt 560 1000 1230 ns current sense amplifier output settle time to 99% (38) , (41) rl = 1k ? , c l = 500pf 0.3 < v o < 4.8v gain = 5 to 15 t settle ? 1.0 2.0 s notes 38. this parameter is guaranteed by design, not production tested. 39. maximum duty cycle is actually 100% bec ause there is an internal charge pump to maintain the gate voltage in the 100% on con dition. however, in high duty cycle cases, there may not be sufficient time to recharge the bootstrap capacitors during the off time. l arge bootstrap capacitors will allow high duty cycles to be obtained for a short time. for applications needing closer to 100% duty cycle, external diodes may optionally be used to provide high peak current charging capability to the bootstrap capacitors. these diod es would be connected between vls and the px_bootstrap pins. in applications with lower gate charge requirements, the maximum duty cycle can also be increased. 40. a minimum deadtime of 0.0 can be set via a spi command. when deadtime is set via a deadtime command, a minimum of 1 clock cycle duration and a maximum of 255 clock cycl es is set using the internal time base clock as a reference. commands exceeding t his value limits at this value. 41. without considering any offsets such as input offset voltage, internal mismatch and assuming no tolerance error in external resistors. table 4. dynamic electrical characteristics (continued) characteristics noted under conditions 8.0v v pwr = v bat 40v, -40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 15 33927 electrical characteristics dynamic electrical characteristics current sense amplifier (continued) output rise time to 90% (43) rl = 1k ? , c l = 500 pf 0.3 < v o < 4.8v gain = 5 to 15 t is_rise ? ? 1.0 s output fall time to 10% (43) rl = 1k ? c l = 500pf 0.3 < v o < 4.8v gain = 5 to 15 t is_fall ? ? 1.0 s slew rate at gain = 5.0 (42) rl = 1 ? , c l = 20pf sr (5) 5.0 ? ? v/s phase margin at gain = 5.0 (42) f m ?30? unity gain bandwidth (42) rl = 1 ? , c l = 100pf g bw ?20?mhz bandwidth at gain = 15 (42) r l = 1 ? , c l = 50pf bw g 2.0 ? ? mhz common mode rejection (cmr) (42) with v in v in_cm = 400mv*sin(2* *freq*t) v in _ dif = 0.0v, rs = 1k ? r fb = 15 k ? , v refin = 0.0v cmr = 20*log(v out /v in _ cm ) freq = 100khz freq = 1.0mhz freq = 10mhz cmr 50 40 30 ? ? ? ? ? ? db supervisory and control circuits en1 and en2 propagation delay t prop ? ? 280 ns int rise time cl = 100 pf t rint 10 ? 250 ns int fall time cl = 100 pf t fint 10 ? 200 ns int propagation time t propint ? ? 250 ns notes 42. this parameter is guaranteed by design, not production tested. 43. rise and fall times are measured from the transition of a st ep function on the input to 90% of the change in output voltage. table 4. dynamic electrical characteristics (continued) characteristics noted under conditions 8.0v v pwr = v bat 40v, -40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 16 freescale semiconductor 33927 electrical characteristics dynamic electrical characteristics spi interface timing maximum frequency of spi operation f op ? 5.0 mhz internal time base f tb 13 17 25 mhz internal time base drift from value at 25 c (44) tc tb -5 ? 5 % falling edge of cs to rising edge of sclk (required setup time) (44) t lead 100 ? ? ns falling edge of sclk to rising edge of cs (required setup time) (44) t lag 100 ? ? ns si to falling edge of sclk (required setup time) (44) t sisu 25 ? ? ns falling edge of sclk to si (required setup time) (44) t sihold 25 ? ? ns si, cs , sclk signal rise time (44) , (45) t rsi ? 5.0 ? ns si, cs , sclk signal fall time (44) , (45) t fsi ? 5.0 ? ns time from falling edge of cs to so low impedance (44) , (46) t soen ? 55 100 ns time from rising edge of cs to so high impedance (44) , (47) t sodis ? 100 125 ns time from rising edge of sclk to so data valid (44) , (48) t valid ? 55 100 ns time from rising edge of cs to falling edge of the next cs (44) t dt 200 ? ? ns notes 44. this parameter is guaranteed by design, not production tested. 45. rise and fall time of incoming si, cs , and sclk signals suggested for design considerat ion to prevent the oc currence of double pulsing. 46. time required for valid output status data to be available on so pin. 47. time required for output states data to be terminated at so pin. 48. time required to obtain valid data out from so following the rise of sclk with 200 pf load. table 4. dynamic electrical characteristics (continued) characteristics noted under conditions 8.0v v pwr = v bat 40v, -40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 17 33927 electrical characteristics timing diagrams timing diagrams figure 4. spi interface timing figure 5. desaturation bl anking and filtering detail figure 6. deadtime control delays t do (dis) 0.7 v dd 0. 2 v dd 0.2 v dd 0.7 v dd 0.2 v dd t lead t di(su) t di(ho ld) t valid t lag cs sclk si so msb in msb out lsb out 0.7 v dd 0.2 v dd t do(en) t sodis t soen t sisu t sihold t lag from delay timer p x _hs p x _ls desaturation fault p x _ls p x _hs en1 en2 rst state deadtime control 1 st pulse machine p x _hs_g p x _hs_s p x _ls_g dq clk d q clk dq clk dq clk dq clk dq clk b out a mux b out a mux
analog integrated circuit device data 18 freescale semiconductor 33927 electrical characteristics timing diagrams figure 7. driver turn-on time and turn-on delay figure 8. driver turn-off time and turn-off delay 50 % px_hs _g px_hs 10v 1.0v t d_onh t onh 50% px_ls_g px_ls 10v 1.0v t d_onl t onl 50% 10v 1.0v t d_offl t offl px_ls_g px_ ls px_hs_g px_hs 50% 10v 1.0v t d_offh t offh
analog integrated circuit device data freescale semiconductor 19 33927 electrical characteristics timing diagrams figure 9. current amplifier and input waveform (v in voltage across r sense ) v in - ref r sense amp_out amp_p amp_n oc_th v id r f bn r fb p r s r s + + - to protection circuits 9 9 p9wrp9 p9wrp9 ?6?6 ?6?6 ?6?6
analog integrated circuit device data 20 freescale semiconductor 33927 functional descriptions introduction functional descriptions introduction the 33927 provides an interface between an mcu and the large fets used to drive three-phase loads. a typical load fet may have an on-resistance of 4.0m ? or less and could require a gate charge of over 400 nc to fully turn on. the ic can operate in automotive 12v to 42v environments. because there are so many methods of controlling three- phase systems, the ic enforces few constraints on driving the fets. it does provide deadtime (cross-over) blanking and logic, both of which can be overridden, ensuring both fets in a phase are not simultaneously enabled. a spi port is used to configure the ic modes. functional pin description phase a (phasea) this pin is the totem pole output of the phase a comparator. this output is low when the voltage on phase a high-side source (source of the high-side load fet) is less than 50 percent of vbat. power ground (pgnd) this pin is power ground for the charge pump. it should be connected to vss, however routing to a single point ground on the pcb may help to isolate charge pump noise. note: this is not the same as the phase grounds for each of the phases. enable 1 and enable 2 (en1, en2) both of these logic signal inputs must be high to enable any gate drive output. when either or both are low, the internal logic (spi port, etc.) still functions normally, but all gate drives are forced off (external power fet gates pulled low). the signal is asynchronous. when en1 and en2 return high to enable the outputs, each ls driver must be pulsed on before the corresponding hs driver can be commanded on. this ensures that the bootstrap capacitors are charged. reset (rst ) when the reset pin is low the integrated circuit (ic) is in a low power state. in this mode all outputs are disabled, internal bias circuits are turned off, and a small pull down current is applied to the output gate drives. the internal logic will be reset within 77ns of r eset going low. when rst is low, the ic will consume minimal current. this input should not be driven above the vdd voltage. charge pump out (pump) this pin is the switching node of the charge pump circuit. the output of the internal charge pump support circuit. when the charge pump is used, it is connected to the external pumping capacitor. this pin may be left floating if the charge pump is not required. charge pump input (vpump) this pin is the input supply for the charge pump circuit. when the charge pump is required, this pin should be connected to a polarity protected supply. typical applications would connect it to vbat. th is input should never be connected to a supply greater than 40v. if the charge pump is not required this pin may be left floating. vbat input (vbat) this pin should be connec ted to the system battery voltage. it is used to provide power to the internal steady state trickle charge pump and to energize the hold-off circuit. it is also the reference bias for the phase comparators and desaturation comparator. phase b (phaseb) this pin is the totem pole output of the phase b comparator. this output is low when the voltage on phase b high-side source (source of the high-side load fet) is less than 50 percent of vbat. phase c (phasec) this pin is the totem pole output of the phase c comparator. this output is low when the voltage on phase c high-side source (source of the high-side load fet) is less than 50 percent of vbat. phase a high-side input (pa_hs ) this input logic signal pin enables the high-side driver for phase a. the signal is active low, and is pulled up by an internal current source. phase a low-side input (pa_ls) this input logic signal pin enables the low-side driver for phase a. the signal is active high, and is pulled down by an internal current sink. vdd voltage regulator (vdd) this pin is an internally generated 5v supply. the internal regulator provides continuous power to the ic and is a supply
analog integrated circuit device data freescale semiconductor 21 33927 functional descriptions introduction reference for the spi port. a 0.47f (min) decoupling capacitor must be connected to this pin. this regulator is intended for internal ic use and can supply only a small (1ma) external load current. a power-on-reset (por) circuit monitors this pin and until the voltage rises above the threshold, the internal logic will be reset; driver outputs will be tri-stated and spi communication disabled. the vdd regulator can be disabled by asserting the rst signal low. the vdd regulator is powered from the vpwr pin. phase b high-side control input (pb_hs ) this pin is the input logic signal, enabling the high-side driver for phase b. the signal is active low, and is pulled up by an internal current source. phase b low-side input (pb_ls) this pin is the input logic signal, enabling the low-side driver for phase b. the signal is active high, and is pulled down by an internal current sink. interrupt (int) the interrupt pin is a totem pole logic output. when a fault is detected, this pin will pull high until it is cleared by executing the clear interrupt command via the spi port. the faults capable of causing an interrupt can be masked via the mask0 and mask1 spi registers to customize the response. chip select (cs ) chip select is a logic input that frames the spi commands and enables the spi port. this signal is active low, and is pulled up by an internal current source. serial in (si) the serial in pin is used to input data to the spi port. clocked on the falling edge of sclk, it is the most significant bit (msb) first. this pin is pulled down by an internal current sink. serial clock (sclk) this logic input is the clock is used for the spi port. the sclk typically runs at 3 mhz (up to 5 mhz) and is pulled down by an internal current sink. serial out (so) output data for the spi port streams from this pin. it is tri- stated until cs is low. new data appears on rising edges of sclk in preparation for latching by the falling edge of sclk on the master. phase c low-side input (pc_ls) this input logic pin enables the low-side driver for phase c. this pin is an active high, and is pulled down by an internal current sink. phase c high-side input (pc_hs ) this input logic pin enables the high-side driver for phase c. this signal is active low, and is pulled up by an internal current source. amplifier output (amp_out) this pin is the output for the current sensing amplifier. it is also the sense input to the overcurrent comparator. amplifier inverting input (amp_n) the inverting input to the current sensing amplifier. amplifier non-inverting input (amp_p) the non-inverting input to the current sensing amplifier. overcurrent comparator output (oc_out) the overcurrent comparator output is a totem pole logic level output. a logic high indicates an overcurrent condition. overcurrent comparator threshold (oc_th) this input sets the threshold level of the overcurrent comparator. voltage source supply (vss) vss is the ground reference for the logic interface and power supplies. ground (gnd0,gnd1) these two pins are connected internally to vss by a 1.0 ? resistor. they provide device substrate connections and also the primary return path for esd protection. vls regulator capacitor (vls_cap) this connection is for a capacitor which will provide a low impedance for switching currents on the gate drive. a low esr decoupling capacitor, capable of sourcing the pulsed drive currents must be connec ted between this pin and vss. this is the same dc node as vls, but it is physically placed on the opposite end of the ic to minimize the source impedance to the gate drive circuits. phase c ground (pgndc) the phase c power ground is the pin used to return the gate currents from the low side fet. best performance is normally realized by connecting this node directly to the source of the low side fet for phase c.
analog integrated circuit device data 22 freescale semiconductor 33927 functional descriptions introduction phase c low-side gate (pc_ls_g) this is the gate drive for the phase c low side output fet. it provides a high current with a low impedance to turn on and off the low side fet. a low impedance drive ensures transient currents do not overcome an off-state driver and allow pulses of current to flow in the external fet. this output has been designed to resist the influence of negative currents also. phase c high-side source (pc_hs_s) the source connection for the phase c high side output fet is the reference voltage for the gate drive on the high side fet and also the low voltage end of the bootstrap capacitor. phase c high-side gate (pc_hs_g) this is the gate drive for the phase c high side output fet. this pin provides the gate bias to turn the external fet on or off. the gate voltage is limited to about 15v above the fet source voltage. a low impedance drive is used, ensuring transient currents do not overcome an off-state driver and allow pulses of current to flow in the external fets. this output has been designed to resist the influence of negative currents also. phase c bootstrap (pc_boot) this is the bootstrap capacitor connection for phase c. a capacitor (typically 0.1f) connected between pc_hs_s and this pin provides the gate voltage and current to drive the external fet gate. the voltage across this capacitor is limited to about 15v. phase b ground (pgndb) the phase b power ground is the pin used to return the gate currents from the low side fet. best performance is normally realized by connecting this node directly to the source of the low side fet for phase b. phase b low-side gate (pc_ls_g) this is the gate drive for the phase b low side output fet. it provides a high current with a low impedance to turn on and off the low side fet. a low impedance drive ensures transient currents do not overcome an off-state driver and allow pulses of current to flow in the external fet. this output has been designed to resist the influence of negative currents also. phase b high-side source (pb_hs_s) the source connection for the phase b high side output fet is the reference voltage for the gate drive on the high side fet and also the low voltage end of the bootstrap capacitor. phase b high-side gate (pb_hs_g) this is the gate drive for the phase b high side output fet. this pin provides the gate bias to turn the external fet on or off. the gate voltage is limited to about 15v above the fet source voltage. a low impedance drive is used, ensuring transient currents do not overcome an off-state driver and allow pulses of current to flow in the external fets. this output has been designed to resist the influence of negative currents also. phase b bootstrap (pb_boot) this is the bootstrap capacitor connection for phase b. a capacitor (typically 0.1f) connected between pb_hs_s and this pin provides the gate voltage and current to drive the external fet gate. the voltage across this capacitor is limited to about 15v. phase a ground (pgnda) the phase a power ground is the pin used to return the gate currents from the low side fet. best performance is normally realized by connecting this node directly to the source of the low side fet for phase a. phase a low-side gate (pa_ls_g) this is the gate drive for the phase a low side output fet. it provides a high current with a low impedance to turn on and off the low side fet. a low impedance drive ensures transient currents do not overcome an off-state driver and allow pulses of current to flow in the external fet. this output has been designed to resist the influence of negative currents also. phase a high-side source (pa_hs_s) the source connection for the phase a high side output fet is the reference voltage for the gate drive on the high side fet and also the low voltage end of the bootstrap capacitor. phase a high-side gate (pa_hs_g) this is the gate drive for the phase a high side output fet. this pin provides the gate bias to turn the external fet on or off. the gate voltage is limited to about 15v above the fet source voltage. a low impedance drive is used, ensuring transient currents do not overcome an off-state driver and allow pulses of current to flow in the external fets. this output has been designed to resist the influence of negative currents also. phase a bootstrap (pa_boot) this is the bootstrap capacitor connection for phase a. a capacitor (typically 0.1f) connected between pa_hs_s and this pin provides the gate voltage and current to drive the external fet gate. the voltage across this capacitor is limited to about 15v.
analog integrated circuit device data freescale semiconductor 23 33927 functional descriptions introduction vls regulator (vls) vls is the gate drive power supply regulated at approximately 15v. this is an internally generated supply from vpwr. it is the source for the low side gate drive voltage, and also the high side bootstrap source. a low esr decoupling capacitor, capable of sourcing the pulsed drive currents, must be connected between this pin and vss or pgnd. vpwr input (vpwr) vpwr is the power supply input for vls and vdd. current flowing into this input recharges the bootstrap capacitors as well as supplying power to the low-side gate drivers and the vdd regulator. an internal regulator regulates the actual gate voltages. this pin can be connected to system battery voltage if power dissipation is not a concern. exposed pad (ep) the primary function of the exposed pad is to conduct heat out of the device. this pad may be connected electrically to the substrate of the devic e.the device will perform as specified with the exposed pad un-terminated (floating). however, it is recommended that the exposed pad be terminated to pin 29 (vss) and the system ground.
analog integrated circuit device data 24 freescale semiconductor 33927 functional internal block description introduction functional internal block description figure 10. functional internal block description all functions of the ic can be described as the following five major functional blocks: ? logic inputs and interface ? bootstrap supply ? low-side drivers ? high-side drivers ? charge pump logic inputs and interface this section contains the spi port, control logic, and shoot- through timers. the ic logic inputs have schmitt trigger inputs with hysteresis. logic inputs are 3v compatible. the logic outputs are driven from the internal supply of approximately 5.0v. when the internal supply is not enabled, the so pin should not be externally driven high. the spi registers and functionality is described completely in the logic commands and registers section of this document. spi functionality includes the following: ? programming of deadtime delay ?this delay is adjustable in approximately 50 ns steps from 0 ns to 12 s. calibration of the delay, because of internal ic variations, is performed via the spi. ? enabling of simultaneous operation of high-side and low-side fets ?normally, both fets would not be enabled simultaneously. however, for certain applications where the load is connected between the high-side and low-side fets, this could be advantageous. if this mode is enabled, the blanking time delay will be disabled. a sequence of commands may be required to enable this function to prevent inadvertent enabling. in addition, this command can only be executed once after reset to enable or disable simultaneous turn-on. ? setting of various operating modes of the ic and enabling of interrupt sources. the 33927 allows different operating modes to be set and locked by a spi command (fullon, desaturation fault, zero-deadtime). spi commands can also determine how the various faults are (or are not) reported. ? read back of internal registers . the status of the 33927 status registers can be read back by the master (dsp or mcu). the px_hs and px_ls logic inputs are edge sensitive. this means the leading edge on an input will cause the complementary output to immediately turn off and the selected one to turn on after the deadtime delay as illustrated in figure 11 . the deadtime delay timer starts when the corresponding fet was commanded off (see figure 6 and figure 11 ). figure 11. edge sensitive logic inputs (phase a) bootstrap supply (vpwr) this is the portion of the ic providing current to recharge the bootstrap capacitors. it also supplies the peak currents required for the low-side gate drivers. the power for the gate drive circuits is provided through the vpwr pin. this pin can be connected to vbat and is capable of withstanding up to the full load dump voltage of the system. however, the ic only requires a low- voltage supply logic inputs bootstrap low-side drivers high-side drivers and interface charge pump supply pa _h s pa_ls pa_ h s_ g pa_ls_g de adt ime de lay
analog integrated circuit device data freescale semiconductor 25 33927 functional internal block description introduction on this pin, typically 15v. higher voltages on the pin increases the ic power dissipation. in 12v systems the supply voltage can fall as low as 6.0v. this limits the gate voltage capable of being applied to the fets and reduces system perf ormance due to the higher fet on-resistance. to allow a higher gate voltage to be supplied, the ic also incorporates a charge pump. the switches and control circuitry are internal; the capacitors and diodes are external (see figure 17 ). low side drivers these three drivers turn on and off the external low side fets. the circuits provide a low impedance drive to the gate, ensuring the fets remain off in the presence of high dv/dt transients on their drains. additionally, these output drivers isolate the other portions of the ic from currents capable of being injected into the substrate due to rapid dv/dt transients on the fet drains. low-side drivers switch power from vls to the gates of the low-side fets. the low-side drivers are capable of providing a typical peak current of 2.0a. this gate drive current may be limited by external resistors in order to achieve a good trade- off between the efficiency and emc (electro-magnetic compatibility) compliance of the application. the low side driver uses high side pmos for turn on and low side isolated ldmos for turn off. the circuit ensures the impedance of the driver remains low, even during periods of reduced current. current limit is blanked immediately after subsequent input state change in order to ensure device stays off during dv/dt transients. high side drivers these three drivers switch the voltage across the bootstrap capacitor to the external high side fets. the circuits provide a low-impedance drive to the gate, ensuring the fets remain off in the presence of high dv/dt transients on their sources. further, these output drivers isolate the other portions of the ic from currents capable of being injected into the substrate due to rapid dv/dt transients on the fets. the high-side drivers deliver power from their bootstrap capacitor to the gate of the external high-side fet, thus turning the high-side fet on. the high-side driver uses a level shifter, which allows the gate of the external high-side fet to be turned off by switching to the high-side fet source. because the gate supply voltage for the high-side drivers is obtained from the bootstrap supply, a short time is required after the application of power to the ic to charge the bootstrap capacitors. to ensure th is occurrence, the internal control logic will not allow a high-side switch to be turned on after entering the enable state until the corresponding low side switch is enabled at least once. caution must be exercised after a long period of inactivity of the low-side switches, to verify the bootstrap capacitor is not discharged. it can be recharged by activating the low-side switches for a brief period, or by attaching external bleed resistors to the hs_s pins to gnd. in order to achieve a 100% duty cycle operation of the high-side external fets, a fully integrated trickle charge pump provides the charge necessary to fully enhance the external fet gates. the slew rate of the external output fet is limited by the driver output impedance, overall (external and internal) gate resistance and the load capacitance. to ensure the low-side fet is not turned on by a large positive dv/dt on the drain of the low side fet, the turn-on slew rate of the high-side should be limited. if the slew rate of the high side is limited by the gate-drain capacitance of the high side fet, then the displacement current injected into the low-side gate drive output will be approximately the same value. therefore, to ensure the low side drivers can be held off, the voltage drop across the low side gate driver must be lower than the threshold voltage of the low side fet (see figure 12 ). similarly, during large negative dv/dt, the high side fet will be able to remain off if its gate drive low side switch, develops a voltage drop less than the threshold voltage of the high side fet. the gate drive low side switch discharges the gate to the source. additionally, during negative dv/dt the low side gate drive could be forced below ground. the low side fets must not inject detrimental substrate currents in this condition. the occurrence of these cases depends on the polarity of the load current during switching. figure 12. positive dv/dt transient
analog integrated circuit device data 26 freescale semiconductor 33927 functional internal block description introduction driver fault protection the 33927 ic integrates several protection mechanisms against various faults. the first of them is the current sense amplifier with the overcurrent comparator. these two blocks are common for all three driver phases. current sense amplifier this amplifier is usually connected as a differential amplifier (see figure 9 ). it senses a current flowing through the external fets as a voltage across the current sense resistor r sense . since the amplifier common mode range does not extend below ground, it is necessary to use an external reference to permit measuring both positive and negative currents. the amplifier output can be monitored directly (e.g. by the microcontroller?s adc) at t he amp_out pin, providing the means for closed loop control with the 33927. the output voltage is internally compared with the overcurrent comparator threshold voltage (see figure 17 ). overcurrent comparator the amplified voltage across the rsense is compared with the pre-set threshold value by the overcurrent comparator input. if the current sense amplifier output voltage exceeds the threshold of the overcurrent comparator it would change the status of its output (oc_out pin) and the fault condition would be latched (see figure 15 ). the occurrence of this fault would be signalled by the return value of the status register 0. if the proper interrupt mask has been set, this fault condition will generate an interrupt - the int pin will be asserted high. the int will be held in the high state until the fault is removed, and the appropriate bit in the status register 0 is cleared by the clint0 command. this fault reporting technique is described in detail in the logic commands and registers section. desaturation detector the desaturation detector is a comparator integrated into the output driver of each phase channel. it provides an additional means to protect against ?short-to-ground? fault condition when the output node gets shorted to the supply voltage (short across the high-side fet). figure 13. short to ground detection when switching from low-side to high-side, the high-side will be commanded on after the end of the deadtime. the deadtime period starts when the low-side is commanded off. if the voltage at p x-hs_s is less than 1.4v below v bat after the blanking time (t blank ) a desaturation fault is initiated. an additional 1ms digital filter is applied from the initiation of the desaturation fault before it is registered, and all phase drivers are turned off (placed in a high impedance state). if the desaturation fault condition clears before the filter time expires, the fault is ignored and the filter timer resets. valid faults are registered in the fault status register, which can be retrieved by way of the spi. additional spi commands will mask the int flag and disable output stage shutdown, due to desaturation and phase errors. see the logic commands and registers section for details on masking int behavior and disabling the protective function.
analog integrated circuit device data freescale semiconductor 27 33927 functional internal block description introduction figure 14. short to battery detection phase comparator faults could also be detected as phase errors . a phase error is generated if the output signal (at px_hs_s) does not properly reflect the drive conditions. a phase error is detected by a phase comparator. the phase comparator compares the voltage at the px_hs_s node with a reference of one half the voltage at the vbat pin. a high side phase error (which will also trigger the desaturation detecto r) occurs when the high side fet is commanded on, and px_hs_s is still low at the end of the deadtime and blanking time duration. similarly, a ls phase error occurs when the low side fet is commanded on, and the px_hs_s is still high at the end of the deadtime and blanking time duration. the phase error flag is the triple or of phase errors from each phase. each phase error is the or of the high side and low side phase errors. this flag can generate an interrupt if the appropriate mask bit is set. the int will be held in the high state until the fault is removed, and the appropriate bit in the status register 0 is cleared by the clint1 command. this fault reporting mechanism is described in detail in the logic commands and registers section. hold off circuit the ic guarantees the output fets are turned off in the absence of v dd or v pwr by means of the hold off circuit. a small current source, generated from vbat, typically 100 a, is mirrored and pulls all the output gate drive pins low when v dd is less than about 3.0v, rst is active (low), or when vls is lower than the vls_disable threshold. charge pump the charge pump circuit provides the basic switching elements required to implement a charge pump when combined with external capacitors and diodes for enhanced low voltage operation. when the 33927 is connected per the typical application using the charge pump (see figure 17 ), the regulation path for vls includes the charge pump and a linear regulator. the regulation set point for the linear regulator is nominally at 15.34v. as long as vls output voltage (vls out ) is greater than the vls analog regulator threshold (vls ath ) minus v threg , the charge pump is not active. if vls out < vls ath ? v threg the charge pump turns on until vls out > vls ath ? v threg + v hyst v hyst is approximately 200mv. vls ath will not interfere with this cycle even when there is overlap in the thresholds due to the design of the regulator system. the maximum current the charge pump can supply is dependent on the pump capacitor value and quality, the pump frequency (nominally 130khz) and the rdson of the pump fets. the effective charge voltage for the pump capacitor would be v bat ? 2*v diode . the total charge transfer would then be c pump * (v bat ? 2*v diode ). multiplying by the switch frequency gives the theoretical current the pump can transfer: f pump * c pump * (v bat ? 2*v diode ). note: there is also another smaller, fully integrated charge pump (trickle charge pump - see figure 2 ), which is used to maintain the high-side drivers? gate v gs in 100 percent duty cycle modes.
analog integrated circuit device data 28 freescale semiconductor 33927 functional device operation operational modes functional device operation operational modes reset and enable the 33927 has three power modes of operation described in table 5 . there are three global control inputs (rst , en1, en2), which together with the status of the vdd and vls, control the behavior of the ic. the operating status of the ic can be described by the following three modes: sleep mode - when rst is low, the ic is in sleep mode. the current consumption of the ic is at minimum. ? standby mode - the rst input is high while one of the enable inputs is low. the ic is fully biased up and operating, all the external fets are actively turned off by both high-side and low-side gate drives. the ic is ready to enter the enable mode. ? enable mode - in order to enter the enable mode (normal mode of operation), and to operate the outputs, the rst input must be high, and both enable inputs en1 and en2 must also be high. ? after entry to enable mode, the ic requires a pulse on px_ls in order to charge the bootstrap capacitor before allowing the px_hs to turn on. this pulse should be about 50 s to guarantee the bootstrap capacitor is charged, but the ic does not enforce this condition. if there is an alternate means of pre-charging the bootstrap capacitor, i.e. an external resistor from px_hs_s to gnd, then a very brief pulse of 1.0 s is sufficient to reset the logic. table 5. functions of rst , en1 and en2 pins rst en1, en2 mode of operation (driver condition) 0 xx sleep mode - in this mode (low quiescent current) the driver output stage is switched-off with a weak pull-down. all error and spi registers are cleared. the inter nal 5.0v regulator is turned off and vdd is pulled low. logic outputs are clamped to gnd. 1 0x x0 standby mode - ic fully biased up and all functions are operating, the output drivers actively turn off all of the external fets. the spi port is functional. logic leve l outputs are driven with low impedance. v dd , charge pump and v ls regulators are all operating. the ic is ready to move to enable mode. 1 11 enable mode - (normal operation). drivers are enabled; output stage s follow the input command. after enable, outputs require a pulse on px_ls before corresponding hs outputs will turn on in order to recharge bootstrap capacitor. all error pin and register bits are active if detected. table 6. functional ratings ( t j =-40c to 150c and supply voltage range v bat = v pwr = 5.0v to 45v, c = 0.47f) characteristic value default state of input pin px_ls, en1, en2, rst , si, sclk, if left open (49) (driver output is switched off, high impedance mode) low (<1.0v) default state of input pin px_hs , cs if left open (49) (driver output is switched off, high impedance mode) high (>2.0v) notes 49. to assure a defined status for all inputs, these pins are internally biased by pull-up/down current sources.
analog integrated circuit device data freescale semiconductor 29 33927 functional device operation logic commands and registers logic commands and registers command descriptions the ic contains internal registers to control the various operating parameters, modes, and interrupt characteristics. these commands are sent and status is read via 8-bit spi commands. the ic will use the last eight bits in a spi transfer, so devices can be daisy-chained. the first three bits in a spi word can be considered to be the command with the trailing five bits being the data. the spi logic will generate a framing error and ignore the spi message if the number of received bits is not eight or if it is not a multiple of eight. after rst , the first spi result returned is status register 0. fault reporting and interrupt generation different fault conditions described in the previous chapters can generate an interrupt - int pin output signal asserted high. when an interrupt occurs, the source can be read from status register 0, which is also the return word of most spi messages. faults are latched on occurrence, and the interrupt and faults are only cleared by sending the corresponding clintx command. a fault that still exists will continue to assert an interrupt. note: if there are multiple pending interrupts, the int line will not toggle when one of the faults is cleared. interrupt processing circuitry on the host must be level sensitive to correctly detect multiple simultaneous interrupt. thus, when an interrupt occurs, the host can query the ic by sending a null command; the return word contains flags indicating any faults not cleared since the clintx command was last written (rising edge of cs ) and the beginning of the current spi command (falling edge of cs ). the null command causes no changes to the state of any of the fault or mask bits. the logic clearing the fault latches occurs only when: 1. a valid command had been received(i.e. no framing error); 2. a state change did not occur during the spi message (if the bit is being returned as a 0 and a fault change occurs during the middle of the spi message, the latch will remain set). the latch is cleared on the trailing (rising) edge of the cs pulse. note, to prevent missing any faults the clintx command should not generally clear any faults without being observed; i.e. it should only clear faults returned in the prior null response. table 7. command list command name description 000 x xxxx null these commands are used to read ic status. these co mmands do not change any internal ic status. returns status register 0-3, depending on sub command. 001 0 xxxx mask0 sets a portion of the interrupt mask using lower four bits of command. a ?1? bit enables interrupt generation for that flag. int remains asserted if uncleared faul ts are still present. returns status register 0. 001 1 xxxx mask1 sets a portion of the interrupt mask using lower four bits of command. a ?1? bit enables interrupt generation for that flag. int remains asserted if uncleared faul ts are still present. returns status register 0. 010x xxxx mode enables desat/phase error mode. enables fullon mode. locks further mode changes. returns status register 0. 011 0 xxxx clint0 clears a portion of the fault latch corresponding to mask0 using lower four bits of command. a 1 bit clears the interrupt latch for that flag. int remains asserted if other unmasked faults are still present. returns status register 0. 011 1 xxxx clint1 clears a portion of the fault latch corresponding to mask1 using lower four bits of command. a 1 bit clears the interrupt latch for that flag. int remains asserted if other unmasked faults are still present. returns status register 0. 100x xxxx deadtime set deadtime with calibration technique. returns status register 0.
analog integrated circuit device data 30 freescale semiconductor 33927 functional device operation logic commands and registers null commands this command is sent by send ing binary 000x xxxx da ta. this can be used to read ic status in th e spi return word. message 000x xx00 reads status register 0. message 000x xx01 through 000x xx11 read additional internal registers. mask command this is the mask for interrupts. a bit set to ?1? enables the corresponding interrupt. because of the number of mask bits, this register is in two portions: 1. mask0 2. mask1 both are accessed with 0010 xxxx and 0011 xxxx patterns respectively. figure illustrates how interrupts are enabled and faults cleared. clint0 and clint1 have the same format as mask0 and mask1 respectively, but the action is to clear the interrupt latch and status register 0 bit corresponding to the lower nibble of the command. interrupt handling figure 15. interrupt handling table 8. null commands spi data bits 76543210 write 000xxx00 reset null commands are described in detail in the status registers section of this document. table 9. mask0 register spi data bits 76543210 write 0010xxxx reset 1111 table 10. mask1 register spi data bits 76543210 write 0011xxxx reset 1111 to status register various faults from clint command from maskx:n register fault net 0 net n int mask bit int clear int source s r latch
analog integrated circuit device data freescale semiconductor 31 33927 functional device operation logic commands and registers mode command this command is sent by sending binary 010x xxxx data. table 11. setting interrupt masks mask:bit description mask0:0 overtemperature on any gate drive output generates an interrupt if this bit is set. mask0:1 desaturation event on any output generates an interrupt if this bit is set. mask0:2 vls undervoltage generates an interrupt if this bit is set. mask0:3 overcurrent error ?if the overcurrent comparator threshold is exceeded, an interrupt is generated. mask1:0 phase error ?if any phase comparator output is not at the expec ted value when an output is command on, an interrupt is generated. this signal is the xor of the phase comparator ou tput with the output drive state, and blacked for the duration of the desaturation blanking interval. in fullon mode, this signal is blanked and cannot generate an error. mask1:1 framing error ?if a framing error occurs, an interrupt is generated. mask1:2 write error after locking. mask1:3 reset event ?if the ic is set or disabled, an interrupt occurs. since the ic will always start from a reset condition, this can be used to test the interrupt mechanism because when the ic co mes out of reset, an interrupt will immediately occur. table 12. mode command spi data bits 76543210 write 0 1 0 0 desaturation fault mode 0 fullon mode mode lock reset 0000 ? bit 0 ? mode lock is used to enable or disable mode lock. if bit 0 is set, changes to the internal registers are disallowed to prevent inadvertent changes. this bit cannot be cleared onc e set. since the mode lock mode can only be set, this bit prevents any subsequent, and likely erroneous, mode, deadtime, or mask register changes from being received. the only way to clear this bit is to reset the ic . if an attempt is made to write to a register when mode lock is enabled, a write error fault is generated. ? bit 1 ? fullon mode. if this bit is set, programmed deadtime control is di sabled, making it is possible to have both high- and low-side drivers in a phase on simultaneously. this could be useful in special applications such as alternator regulators, or switched-reluctance motor drive applications. there is no deadtime control in fullon mode. input signals directly control the output stages, synchronized with the internal clock. this bit is a ?0?, after reset. until over written, the ic operates nor mally; deadtime control and logic prevents both outputs from being turned on simultaneously. ? bit 3 ? desaturation fault mode controls what happen when a desaturation event is detected. when set to ?0?, any desaturation on any channel causes all six output drivers to shutoff. the drivers can only be re-enabled by executing the clint command. when 1, desaturation faults are completely ignored. bit 3 controls behavior if a desaturation, or phase error event is detected. the possibilities are: ? 0: default: when a desaturation, or phase error event is detected on any channel, all channels turn off and generates an interrupt, if interrupts are enabled. ? 1: disable: desaturation /phase error channel shutdown is disabled, but interrupts are still possible if unmasked. sending a mode command and setting the mode lock simultaneously are allowed. this sets the requested mode and locks out any fur ther changes.
analog integrated circuit device data 32 freescale semiconductor 33927 functional device operation logic commands and registers deadtime command deadtime prevents the turn-on of both transistors in the same phase until the deadtime has expired. the deadtime timer starts when a fet is commanded off (see figure 6 and figure 11 ). the deadtime control is disabled by enabling the fullon mode. the deadtime is set by sending the deadtime command (100x xxx1), and then sending a calibration pulse of cs . this pulse must be 16 times longer than the required deadtime (see figure 16 ). deadtime is measured in cycle times of the internal time base, f tb . this measurement is divided by 16 and stored in an internal register to provide the reference for timing the deadtime between high and low gate transactions in the same phase. for example: the internal time base is running at 20mhz and a 1.5 s deadtime is required. first a deadtime command is sent (using the spi), then a cs is sent. the cs pulse is 16*1.5=24 s wide. the ic measures this pulse as 24000ns/50ns = 480 clock cycles and stores 480/16=30 in the deadtime register. until the next deadtime calibration is performed, 30 clock cycles will separate the turn off and turn on gate signals in the same phase. the worst case error immediately after calibration will be +0/-1 time base cycle, for this example +0ns/-50ns. note that if the internal time base drifts, the effect on dead time will scale directly. sending a zero deadtime command (100x xxx0) sets the deadtime timer to 0. however, simultaneous turn-on of high-side and low-side fets in the same phase is still prevented unless the fullon command has been transmitted. there is no calibration pulse expected after receiving the zero deadtime command. after reset, deadtime is set to the maximum value of 255 time base cycles (typically 15 s). the ic ignores any spi data that is sent during the calibration pulse. if there are any transitions on si or sclk while the deadtime cs pulse is low, a framing error will be generated, however, the cs pulse will be used to calibrate the deadtime figure 16. deadtime calibration table 13. .deadtime command spi data bits 76543210 write 100xxxxzero/ calibrate reset xxxx cs sclk si so deadtime command deadtime calibration pulse
analog integrated circuit device data freescale semiconductor 33 33927 functional device operation logic commands and registers status registers after any spi command, the status of the ic is reported in the return value from the spi port. there are four variants of the null command used to read various status in the ic. other commands return a general status word in the status register 0. there are four status registers in the ic. status register 0 is most commonly used for general status. registers one through three are used to read or confirm internal ic settings. status register 0 (status latch bits) this register is read by sending the null0 command (000x xx00). it is also returned after any other command. this command returns the following data: table 14. status register 0 spi data bits 76543210 results register 0 read reset event write error framing error phase error overcurrent low vls desat detected on any channel tlim detected on any channel reset 10000000 all status bits are latched. the latches are cleared only by se nding a clint0 or clint1 command with the appropriate bits set. if the status is still present, that bit will not clear. clint0 and clint1 have the same format as mask0 and mask1 respectively. ? bit 0 ?is a flag for overtemperature on any channel. this bit is the or of th e latched three internal tlim detectors.this flag can generate an interrupt if the appropriate mask bit is set. ? bit 1 ?is a flag for desaturation detection on any channel. this bit is the or of the latched three internal high-side desaturation detectors and phase error logic. faults are also detected on the low-side as phase errors. a phase error is generated if the output signal (at px_hs_s) does not properly reflect the drive conditions. the phase error is the triple or of phase errors from each phase. each phase error is the or of the hs and ls phase errors. an hs phase error (which will also trigger the desaturation detector) occurs when the hs fet is commanded on, and the px_hs_s is still low in the deadtime duration after it is driven on. similarly, a ls phase error occurs when the ls fet is commanded on, and the px_hs_s is still high in the deadtime duration after the fet is driven on. this flag can generate an interrupt if the appropriate mask bit is set. ? bit 2 ? is a flag for low supply voltage . this bit is latched, thus a prior low voltage event is returned once before being cleared on read. this flag can generate an interrupt if the appropriate mask bit is set. ? bit 3 ?is a flag for the output of the overcurrent comparator . this flag can generate an interrupt if the appropriate mask bit is set. ? bit 4 ?is a flag for a phase error . if any phase comparator output is not at the expected value when just one of the individual high- or low-side outputs is enabled, the fault flag is set. this signal is the xor of the phase comparator output with the output driver state, and blanked for the duration of the desaturation blanking interval. this flag can generate an interrupt if the appropriate mask bit is set. ? bit 5 ?is a flag for a framing error . a framing error is a spi message not a multiple of eight bits (a 0-length message is also a framing error), or si, or sclk toggling detected while measuring the deadtime calibration pulse. this would typically be a transient or permanent hardware error, perhaps due to no ise on the spi lines. this flag can generate an interrupt if the appropriate mask bit is set. ? bit 6 ?indicates a write error after the lock bit is set. a write error is any atte mpted write to the maskn, mode, or a deadtime command after the mode lock bit is set. a write erro r is any attempt to write any other command than the one defined in the table 7 . this would typically be a software error. this flag can generate an interrupt if the appropriate mask bit is set. ? bit 7 ?is set upon exiting rst . it can be used to test the interrupt mechanism or to flag for a condition where the ic gets reset without the host being otherwise aware. this flag can generate an interrupt if the appropriate mask bit is set.
analog integrated circuit device data 34 freescale semiconductor 33927 functional device operation logic commands and registers status register 1 (mode bits) this register is read by sending the null1 command (000x xx01) . this is guaranteed to not affect ic operation and returns the following data: status register 2 (mask bits) this register is read by sending the null2 command (000x xx10) . this is guaranteed to not affect ic operation and returns the following data: status register 3 (deadtime) this register is read by sending the null3 command (000x xx11) . this is guaranteed to not affect ic operation and returns the following data: table 15. status register 1 spi data bits 76543210 results register 1 read 0 desaturation mode zero deadtime set calibration overflow deadtime calibration 0 fullon mode lock bit reset 00000000 ? bit 0 ? lock bit indicates the ic registers (deadtime, maskn, clin tn, and mode) are locked. any subsequent write to these registers is ignored and will set the write error flag. ? bit 1 ? is the present status of fullon mode . if this bit is set to ?0?, the fullon mode is not allowed. a ?1? indicates the ic can operate in fullon mode (both high-side and low-side fets of one phase can be simultaneously turned on). ? bit 3 ?indicates deadtime calibration occurred. it will be ?0? until a successful deadtime command is executed. this includes the zero deadtime setting, as well as a calibration overflow. ? bit 4 ?is a flag for a deadtime calibration overflow . ? bit 5 ?is set if zero deadtime is commanded. ? bit 6 ?reflects the current state of the desaturation/phase error turn-off mode. table 16. status register 2 spi data bits 76543210 results register 2 read mask1:3 mask1:2 mask1:1 mask1:0 mask0:3 mask0:2 mask0:1 mask0:0 reset 11111111 table 17. status register 3 spi data bits 76543210 results register 3 read dead7 dead6 dead5 dead4 dead3 dead2 dead1 dead0 reset 00000000 these bits represent the calibration applied to the internal oscillator to generate the requested deadtime. if calibration is n ot yet performed, all these bits return 0 even though the actual dead time is the maximum.
analog integrated circuit device data freescale semiconductor 35 33927 functional device operation logic commands and registers ic initialization here is a possible flow to initialize the ic and its software environment. 1. apply power (vbat) to module 1.1. this doesn?t wake-up the ic because vpump isn?t powered. vbat current will be low because it will only be leakage and the small hold off bias current. 2. power-up vpump 2.1. no changes will occur until rst rises 3. remove rst (en1 and en2 are still low) 3.1. as the module powers up, rst will rise, allowing the ic to power-up. the charge pump will start, and vpwr and vls will stabilize. 3.2. vdd will rise as the internal regulator charges the external reservoir capacitor and the ic will come out of reset. 3.3. initialize interrupt handler for mcu 3.4. interrupt will occur because of the reset (interrupt processing will occur here) 4. initialize registers 4.1. initialize mask register by sending 0010 xxxx or 0011 xxxx to mask out unwanted interrupts. 4.2. send mode command with desired bits, and also the lo ck bit. e.g. 01000001. this prevents further mode changes. 5. bring en1 & en2 high 5.1. this fully enables the ic main loop 1. while (forever) 1.1. send spi messages (except null1-3), read results 1.2. if sending null1-3 messages, use a semaphore to detect interrupts 1.2.1. set semaphore flag in ram 1.2.2. send null1-3 1.2.3. send null0, read sr1-3 1.2.4. if semaphore is still set, then result is good, else go to 1.2.1 (because an interrupt has gotten in the way) 1.2.5. clear semaphore 2. end interrupt handler when an interrupt occurs, the general procedure is to send null0 and null1 commands to determine what happened, take corrective action (if needed), clear the fault and return. because the return value from a spi command is actually retu rned in the subsequent message, main-loop software that tries to read sr1, sr2 or sr3, may experience an interrupt betwe en sending the spi command and the subsequent read. thus if these registers are to be read, special care must be taken in the software to ensure that the correct results are being interpr eted. 1. interrupt service routine: 1.1. disable further interrupts from 33927 1.2. clear semaphore in 1.2.1 of main loop. this indicates to the main loop that an interrupt occurred and that the return value it gets may not be as expected. 1.3. send null0 command. ignore return value, since this will have been associated with some unknown previous command 1.4. send null0 command. the return value will be sr0 from the previous null0 command 2. process bits in sr0 and correct any faults 3. send clint0 command to clear known (i.e. processed faults from sr0) faults 0:3 4. send clint1 command to clear processed faults 4:7. note, the return sr0 register from this command is actually read in the main routine. 5. re-enable interrupts from the 33927 6. return
analog integrated circuit device data 36 freescale semiconductor 33927 functional device operation protection and diagnosis features protection and diagnosis features table 18. 33927 fault protection no. fault cause detection 33927 protective action 1 phase output shorted to vbat (high-side fet shorted) wire harness shorted to battery drain-to-source short on the high-side fet ? directly sensed by adc as voltage across r sense ? overcurrent comparator output oc_out monitoring (overcurrent error) ? low-side phase error ? direct phasex output monitoring ? all external fets turned off ? fault bit set in status register ? int pin set high ? oc_out pin set high 2 phase output shorted to ground (r sense bypassed) wire harness shorted to battery ? desaturation error ? high-side phase error ? direct phasex output monitoring ? all external fets turned off ? fault bit set in status register ? int pin set high 3 low-side fet shorted drain-to-source short on the low-side fet ? directly sensed by the adc as voltage across r sense ? overcurrent comparator output oc_out high (overcurrent error) ? desaturation error ? high-side phase error ? direct phasex output monitoring ? all external fets turned off ? fault bit set in status register ? int pin set high ? oc_out pin set high 4 high-side fet opened module board assembly issue ? desaturation error ? high-side phase error ? all external fets turned off ? fault bit set in status register ? int pin set high 5 low-side fet opened module board assembly issue ? directly sensed by adc as voltage across r sense ? low-side phase error ? all external fets turned off ? fault bit set in status register ? int pin set high 6 phase output opened (no load) wire harness open ? directly sensed by adc as voltage across r sense note: other protective actions should be taken at the system level by the controlling microcontroller or dsp. it is possible to disable all automatic shutdowns except for vls undervoltage. even when masked, faults will be registered by the status registers.
analog integrated circuit device data freescale semiconductor 37 33927 typical applications protection and diagnosis features typical applications figure 17. typical application diagram using charge pump (+12v battery system) vpump pump vbat vpwr vls vdd px_hs px_ls phasex cs si sclk so rst int amp_p amp_n amp_out pgndx main charge pump pgnd en1 en2 oc_out gnd(2) px_boot px_hs_g px_hs_s px_ls_g oc_th vls_cap trickle charge pump hold -off circuit oscillator control logic 5v reg. vdd vls reg. uv detect t-lim + - + - + - 1.4v + - vbat vbat + - over-cur. comp. i-sense amp. high- side driver low- side driver 3 3 3 3x desat. comp phase comp. vss v bat +12v nom. to adc to other two phases phase x output to motor phase return r sense c x_boot r g_hs (optional) (optional) r g_ls +
analog integrated circuit device data 38 freescale semiconductor 33927 typical applications protection and diagnosis features figure 18. high-voltage application diagram (+42v battery system) vpump pump vbat vpwr vls vdd px_hs px_ls phasex cs si sclk so rst int amp_p amp_n amp_out pgndx main charge pump pgnd en1 en2 oc_out gnd(2) px_boot px_hs_g px_hs_s px_ls_g oc_th vls_cap trickle charge pump hold -off circuit oscillator control logic 5v reg. vdd vls reg. uv detect t-lim + - + - + - 1.4v + - vbat vbat + - over-cur. comp. i-sense amp. high- side driver low- side driver 3 3 3 3x desat. comp phase comp. vss v bat +42v nom. to adc to other two phases phase x output to motor phase return r sense c x_boot r g_hs (optional) (optional) r g_ls + +14v nom.
analog integrated circuit device data freescale semiconductor 39 33927 typical applications protection and diagnosis features figure 19. power dissipation profile of application using charge pump reference application with: ? pump capacitor: 1 f mlc ? pump filter capacitor: 47 f low esr aluminum electrolytic ? pump diodes: mur120 ? output fet gate charge: 240 nc @ 10v ? pwm frequency: 20khz ? switching single phase below approximately 17v the charge pump is actively regulating vpwr. the increased power dissipation is due to the charge pump losses. above this voltage the charge pump oscillator shuts do wn and vbat is passed through the pump diodes directly to vpwr.
analog integrated circuit device data 40 freescale semiconductor 33927 protection and diagnosis features figure 20. power dissipation profile of application not using charge pump reference application with: ? output fet gate charge: 240 nc @ 10v ? pwm frequency: 20khz ? switching single phase ? no connections to pump or vpump ? vpwr connected to vbat if vpwr is supplied by a separate pre-regulator, the power dissipati on profile will be nearly flat at the value of the pre-regu lator voltage for all vbat voltages.
analog integrated circuit device data freescale semiconductor 41 33927 packaging packaging dimension packaging packaging dimension for the most current package revision, visit www.freescale.com and perform a keyword search using the ?98a? listed below. ek suffix (pb-free) 54-pin 98asa99334d issue c
analog integrated circuit device data 42 freescale semiconductor 33927 packaging packaging dimension (continued) packaging dimension (continued) ek suffix (pb-free) 54-pin 98asa99334d issue c
analog integrated circuit device data freescale semiconductor 43 33927 revision history revision history revision date description of changes 2.0 8/2007 ? initial release
mc33927 rev. 2.0 8/2007 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its produ cts for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically disclai ms any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specificati ons can and do vary in different applications and actual perf ormance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of ot hers. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized us e, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are tr ademarks of freescale semiconductor, inc. all other product or service names are t he property of their respective owners. ? freescale semiconductor, inc., 2007. all rights reserved. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com

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